1. Field of the Invention
The present invention relates to a gate circuit, more particularly to a gate circuit constituted, for example, by a set of a transistor-coupled transistor logic (TTL) and a diode-transistor logic (DTL), which is advantageously used in a microcomputer system.
2. Description of the Related Art
As is well known, in a microcomputer system, a plurality of interface circuits are provided between a central processing unit (CPU) and a read-only memory (ROM), random-access memory (RAM), and input/output (I/O) unit through a data bus line. Each interface circuit has, for example, a plurality of set/reset latch circuits (SRL circuit) for controlling the writing or holding of data transmitted to the CPU. The timing for writing or holding data is controlled by an inverted strobe signal and a non-inverted strobe signal, each generated from the gate circuit. The gate circuit applies these signals in parallel to each of the SRL circuits. The SRL circuits are necessary to maintain a high level output at both "write" and "hold" modes in spite of a change of any strobe signals.
In the gate circuit, when the strobe signal is changed, for example, from a low level to a high level, the inverted signal is turned from a high level to a low level and the non-inverted signal is changed from the low level to the high level.
However, when the non-inverted signal is changed from the low level to the high level, there is a time lag in the changeover timing compared to the timing of the inverted signal. Therefore, there is an unexpected case wherein the non-inverted signal and the inverted signal are both low level simultaneously.
Due to this timing, a so-called "glitch" noise occurs from the output of the SRL circuits. This glitch noise results in data errors in the CPU and other circuits.